Nehalem is the codename for a future processor microarchitecture being developed by Intel[1]. Nehalem will be released in late 2008 for high-end chips[2] and Q3 2009 for mainstream chips. [1] The microarchitecture is the planned successor to the Core microarchitecture.
Nehalem uses the 45 nm manufacturing methods from Penryn and applies it to the new Nehalem microarchitecture. A working system with two Nehalem processors was shown at Intel Developer Forum Fall 2007[3], and a large number of Nehalem systems were shown at Computex in June 2008.
The processor is named after the Nehalem River in Northwest Oregon, which is in turn named after the Nehalem Native American tribe in Oregon. The code name itself had been seen on the end of several roadmaps starting in 2000. At that stage it was supposed to be the latest evolution of the NetBurst architecture. Since the abandonment of NetBurst, the codename has been recycled and refers to a completely different project.
As of its current de_script_ion (at Spring IDF 2008), Nehalem appears to incorporate the most significant new architectural changes to the x86 microarchitecture since the Pentium Pro debuted in 1995. Nehalem is highly scalable with different components for different tasks. Various sources have stated Nehalem's specification will have:
* 2, 4, or 8 cores.
o 731 million transistors for the quad core variant.
* 45 nm manufacturing process.
* Integrated memory controller supporting DDR3 SDRAM and between 1 and 6[citation needed] memory channels.
* Integrated graphics processor (IGP) located off-die, but in the same CPU package.[4]
* A new point-to-point processor interconnect, the Intel QuickPath Interconnect, replacing the legacy front side bus.
* Hyper-threading, which enables two threads per core. HyperThreading has not been present on a consumer Intel processor since 2006 with the Pentium 4 and Pentium EE.
* Native (monolithic, i.e. all processor cores on a single die) quad and octo (8) core processors.[5]
* 32 KB L1 instruction and 32 KB L1 data cache per core.
* 256 KB L2 cache per core.
* 2 MB L3 cache per core, shared by all cores.
* 33% more in-flight micro-ops than Core.[6]
* 2nd level branch predictor and 2nd level Translation Lookaside Buffer.[6]
* Modular blocks of components such as cores that can be added and subtracted for varying market segments.[7]
Event demonstrations at the Shanghai Intel Developer Forum showed A1 silicon Bloomfield-_base_d Nehalem processors at IDF at a fast 3.2 GHz. This processor has 32 KB L1 instruction and 32 KB L1 data cache, 256 KB L2 cache per core, and 8 MB of shared L3 cache.[8]
It has been reported that Nehalem will have a focus on performance, which accounts for the increased core size.[9] Compared to Penryn, Nehalem will have:
* 1.1x to 1.25x the single-threaded performance or 1.2x to 2x the multithreaded performance at the same power level
* 30% lower power usage for the same performance
* According to a preview from AnandTech "expect a 20 - 50% overall advantage over Penryn with only a 10% increase in power usage. It looks like Intel is on track to delivering just that in Q4."[10]
PC Watch found that a Nehalem "Gainestown" processor has 1.6x the SPECint_rate2006 integer performance and 2.4x the SPECfp_rate_2006 floating-point performance of a 3.0 GHz Xeon X5365 "Clovertown" quad-core processor.[9]
A 2.93 GHz Nehalem "Bloomfield" system has been used to run a 3DMark Vantage benchmark and gave a CPU score of 17966. This information has subsequently been removed due to a NDA. A 2.4 GHz Core 2 Duo E6600 scores 4300 points on 3DMark Vantage.[11] AnandTech used a similar system and found the copy bandwidth using triple-channel 1066 MHz DDR3 was 12.0 GB/s. A 3.0 GHz Core 2 Quad system using dual-channel 1066 MHz DDR3 achieved 6.9 GB/s.[12]
Overclocking Nehalem processors will only be possible with the X58 chipset. The mainstream PCH will not be capable of overclocking unless a hardware mod is found.
Intel says nehalem is ready for 2nd half 2008.
So anyone is ready for this?
Favoured: 0
'm ready dude.. but no money, how?
